In a cache coherent memory system, a processor must read a copy of a cache line into its cache before it can store results anywhere in that cache line. Frequently, however, the processor will write new data into all locations of the cache line and obliterate all of the data read from memory. In such a situation, there was no advantage to having this data initially transferred from the memory. To avoid this, processors typically implement read without data operations which take the form of prefetch instructions that do not require a transfer of data. However, a prefetch instruction explicitly alters the data as the processor will fill in the cache line with zeroes. As a result, an associated compiler must be careful not to issue prefetch instructions outside of a destination array. This could complicate code generation since each prefetch instruction must be issued several loop iterations before the instructions that actually store data into the cache line. A typical simple loop would prefetch beyond an end of an array. This would not be acceptable for general use of a prefetch and zero type of instruction that modifies the cache line it prefetches since modification is being performed outside of the array.